In wafer scale integrated circuits, separate component chips may be individually integrated with a host wafer using any of several established methods for chip level integration.
The alignment accuracy is a critical parameter in determining the utility of this technology. The accuracy of alignment directly impacts the integration densities, interconnect line widths and pitches, and the ability to fabricate 3D stacks of chips. Furthermore, in cooperative radiating or detecting systems, alignment is critical to the functionality of the system.
To insure proper placement and registration of the microstructures, the microstructures are formed as geometric blocks and recesses are etched from the wafer to provide receptacle sites with geometric profiles that are complementary to the profiles of the blocks. One example is shown in U.S. Pat. No. 5,545,291, by Smith et al., entitled METHOD FOR FABRICATING SELF-ASSEMBLING MICROSTRUCTURES, herein incorporated by reference in its entirety. Fluidic self-assembly may be used to integrate the individual device microstructures into receptacle sites on host electronic circuits using a liquid medium for transport. Placement and registration of the device microstructures into receptacles on a substrate carrying electronic microcircuits is controlled by shape recognition or by selective chemical adhesion or both.
Other examples of microstructure placement techniques and structures include U.S. Pat. No. 7,223,635 by Brewer, entitled ORIENTED SELF-LOCATION OF MICROSTRUCTURES WITH ALIGNMENT STRUCTURES; and U.S. Pat. No. 7,018,575, by Brewer et al., entitled METHOD FOR ASSEMBLY OF COMPLEMENTARY-SHAPED RECEPTACLE SITE AND DEVICE MICROSTRUCTURES; both herein incorporated by reference in their entireties. Further examples may be found in U.S. Pat. Nos. 6,946,322 and 5,783,856, herein incorporated by reference.